The TimingAnalyzer¶

9/9/13 Beta version 0.970 is Released.¶

• New “Add Pulse” AP mode button in toolbar. When “Add Pulse” mode is enabled, you can add pulses or edges to any signal in the diagram. The Buttons for H L Z X B are disabled when “Add Pulse” mode is disabled.
• New “Show Hidden” button in the toolbar. Use this to show any hidden Pulse Width Labels, Constraints, or Delays. Use the pop-up menu to un-hide any selected hidden object. Use the pop-up menu to hide the object. The hidden objects are shown with a yellow background.
• Selected objects are shown with dashed line red rectangle around the border. Use toolbar buttons to change color, font, and line styles and see the results immediately
• New font select combobox and button in toolbar. You can easily change the font used for any text selected in the diagram with one click.
• Added Differential Driver. Given an input signal, it creates differential signals. Delays from the original input signal can be added to model path delays or skew on each signal.
• Added “Sync Clock” to DigitalSignal and DigitalBus. When adding pulses to a Signal or Bus, the clock above the signal is used by default if the Synchronous Clock is not specified. For example: How can I model clock tree skew? Add a Differential Driver with a DigitalClock named CLK as the input. Specify delays on both outputs CLK+ and CLK- to represent the different path delays and skew. Sounds like a good idea for another application note.
• Updated the Python API. Updated functions with more consistent argument positions for addDigitalClock, addDigitalBus, and addDigitalSignal. This will break older scripts but the changes are very simple.

The following functions are recommended when adding signals to a timing diagram.

• dclk = timDiagram.addDigitalClock(name, startState, freq)
• dclk = timDiagram.addDigitalClock(name, startState, freq, dutyCyle)
• dclk = timDiagram.addDigitalClock(name, startState, freq, dutyCyle, riseTime, fallTime)
• dsig = timDiagram.addDigitalSignal(name, startState)
• dsig = timDiagram.addDigitalSignal(name, startState, riseTime, fallTime)
• dbus = timDiagram.addDigitalBus(name, startState, stateFormat)
• dbus = timDiagram.addDigitalBus(name, startState, stateFormat, riseTime, fallTime)
• The following functions have been removed.

The following functions have been removed.

• timDiagram.addDigitalClock(dclk)
• timDiagram.addDigitalSignal(dsig)
• timDiagram.addDigitalBus(dbus)

• Fixed addTimeWarp script function.
• Plus other minor fixes and improvements.

5/2/13 Beta Version 0.960 is Released.¶

• PulseWidthLabels, Text Labels, Constraints and Delays can moved across TimeWarps.
• New Toolbar for quick way to add and edit edges and bus values.
• Improved drawing algorithm with TimeWarps improves diagram load times and allows start times greater than 0.
• Diagrams can start at a time greater than 0. This fixes a problem related to the scripts for the VHDL and Verilog monitors that were described in the app notes. If you captured signals from time t1 to time t2, the first edge would be wrong if t1 was not 0.
• Added more error checking for edges that were moved and ended up at a time that is less than zero. This can happen when move multiple edges at one time.
• Removed number of edges for each signal in the .tim file.
• Other fixes and improvements

3/1/13 Beta Version 0.958 Is Coming.¶

Below is preliminary list of changes so far. Much more coming.

• PulseWidthLabel can moved across TimeWarps. Once verified by users, this will be added to Delays and Constraints.
• Added more error checking for edges that were moved and ended up at a time that is less than zero. This can happen when move multiple edges at one time.
• Removed number of edges for each signal in the .tim file.

8/16/11¶

The script below can be used to generate a differential signal. It will be included in the distribution of the next version beta 0.957. Just select clocks or signals in the timing diagram and then run the script. It will add the differential signals for each selected signal. Save the script below as diff_signal.py and put in the scripts directory so it can be executed from the program script panel:

import ta_utils
from org.dmad.ta import DigitalBus

td = taApp.getTimingDiagram()

selected_signal_list = td.getEditSigList()

for selected_signal in selected_signal_list:
    if not isinstance(selected_signal, DigitalBus):
        diff_signal = td.addDigitalSignal(selected_signal.getName() + "_diff",
                                          ta_utils.invert(selected_signal.getStartState()))
        for sig_edge in selected_signal.getEdgeList():
            diff_signal.addEdge(sig_edge.getPt2Min(),ta_utils.invert(sig_edge.getNextState()))

Add the following function to ta_utils.py. It is called in diff_signal.py above:

def invert(state):
    states = {
        "H": "L",
        "1": "L",
        "L": "H",
        "0": "H",
        "Z": "Z"
    }
    return states.get(state)

5/12/11¶

Started a new timing diagram library. A place to hold scripts that generate timing diagrams for commonly used interfaces.

5/1/11¶

Added a FAQ. A place to look for answers to commonly asked questions.

2/5/11¶

Added new documentation. A scripting reference manual reference manual. Both are available in html and pdf. A users guide is coming.

9/29/10¶

Added move signal up and down buttons on the toolbar.

Jython scripts now use the standard libraries without the need for installing jython. The standalone jython.jar archive includes the standard libs, and is included in the jlib directory. When executing scripts from the File → Scripts menu, the interpreter is started and the os and sys libs are imported before executing the selected script file. You can also run scripts from the command line shell or dos window using the following commands:

c:\Apps\TimingAnalyzer_b951> java -jar jlib\jython.jar
...
>>>execfile('start_app.py')
>>>execfile('./scripts/dump_edges.py')

2/6/10¶

The newest feature is ability to read VCD files and convert it to a timing diagram automatically. I have tested with Xilinx Chipscope and Modelsim VCD files. Modelsim VCD files don’t seem to contain buses so I added a function, “Bus Signals” to make buses from sequentially ordered signals like ADIO<31>, ADIO<30>, ADIO<29> … You have to hold the shift key and click on each signal to select multiple signals. Better signal group selections will be addressed in the next version. Selecting groups of signals will only take 2 clicks.

Refer to the documentation for more information

1/24/10¶

Added “Generate Timing Diagrams from Verilog Simulations” Application Note. This app note shows how to use Verilog to generate timing diagrams by writing text files which are Python scripts that the TimingAnalyzer executes to draw the diagram. A separate module in the example, sram_timing_diagram.v, includes all the source code use to generate the Python script. You can read it and download the example at: Generate Timing Diagrams from Verilog Simulations

12/15/09¶

Updated the “Generate Timing Diagrams from VHDL Simulations” Application Note. A separate component, sram_timing_diagram.vhd, is now used to generate the timing diagram Python script. Start and end time are specified as generic parameters so you can make timing diagrams of any window in time from the simulation. This could be used as a template and modified to generate timing diagrams for any interface. A python script could developed that automatically builds this file for given list of signals, anyone interested?

12/1/09¶

Added app notes that explain how to build timing diagrams directly from VHDL or Verilog. Refer to Generate Timing Diagrams from VHDL Simulations and Generate Timing Diagrams from Verilog Simulations

Moving Transactions Synchronously¶

Moving transactions synchronously can make life much easier when you have add signal changes or transactions to an existing timing diagram. For example, if you decide to add a read cycle in between two write cycles you would need to move the 2nd write cycle to the right by maybe 10 clock cycles. This is done with synchronous moves. Simply select the 2nd write cycle by dragging the mouse around the transaction, then use Alt and Right Key combination to move it.

See the video shown below to see an example.

Move Synchronoulsy Video.

Installing the TimingAnalyzer¶

• Download and install the JRE Version 1.6.0 or newer if needed.

• Download the zip file.

• Unzip the downloaded TimingAnalyzer_bxx.zip in any directory:

  c:\Apps\TimingAnalyzer_bxx
        TimingAnalyzer.jar     --   The executable program
        start_app.py           --   Python script to start the program
        scripts                --   directory for user scripts
        examples               --   directory for timing diagram examples
        settings               --   directory for default and user settings
  

Running the TimingAnalyzer¶

• Windows Desktop
  • Make shortcut icon of TimingAnalyzer.jar on Desktop.
  • Double click TimingAnalyzer.jar icon on Desktop.
• Dos Window
  • cd c:\Apps\TimingAnalyer_bxx
  • java -jar TimingAnalyzer.jar

System Requirements¶

• Oracle Java JRE1.6.0 or JDK1.6.0 or newer.
• Windows XP, Vista, Linux, and OS X.

The Timing Diagram Specifications¶

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Start a New Timing Diagram¶

• To start a diagram, File Menu -> New or Ctrl-n

  1. Start a new timing diagram.

Add the User Defined Constraints and Delays.¶

• To add a User Delay, Add Menu -> Delay or Ctrl-7, select User Delay tab in panel.

• To add a User Constraint, Add Menu -> Constraint or Ctrl-8, select User Constraint tab in panel.

  1. Add the Delays shown above.
  2. Add the Constraints shown above.

Adding the Signals¶

• To add a Clock, Add Menu -> Clock or Ctrl-1

• To add a Signal, Add Menu -> Signal or Ctrl-2

• To add a Bus, Add Menu -> Bus or Ctrl-3

  1. Add Clock CLOCK.
  2. Add Bus ADD.
  3. Add Signal CS*.
  4. Add Bus DATA.
  5. Add Signal RD_STROBE*.
  6. Add Signal WR_STROBE*.

Adding the Pulses to the Signals¶

• To enable “Add Pulse” mode, click on AP button. Button background color turns dark.

• To disable “Add Pulse” mode, click on AP button. Button background color turns light.

  1. Enable “Add Pulse” mode.
  2. Set “Auto Increment” in toolbar to 0.
  3. Set signal value in toolbar to FFC0.
  4. Click in ADD bus at 30ns,50ns, and 70nS. This will make a FFC0 pulse for 3 clock cycles.
  5. Select “L”. Click in CS* at 50nS and 70nS. This will make a low pulse for 2 clock cycles.
  6. Change signal value to 55. Click in DATA bus at 70nS. This will make a 55 pulse for 1 clock cycle.
  7. Select “L”. Click in RD_STROBE* at 70nS. This will make a low pulse for 1 clock cycle.
  8. Disable “Add Pulse” mode.

Adding the Delays and Constraints¶

• To add a Delay, Add Menu -> Delay or Ctrl-7 or right button click for pop-up menu

• To add a Constraint, Add Menu -> Constraint or Ctrl-8 or right button click for pop-up menu

• To add a previously used Delay, right button click for pop-up menu and select “Add Used Delay”

• To add a previously used Constraint, right button click for pop-up menu and select “Add Used Constraint”

  1. Select 1st rising edge of CLOCK and 1st edge of ADD. Add delay tclk2add.
  2. Select 1st edge of ADD and 1st edge of CS*. Add delay tpd.
  3. Select 1st edge of CS* and 1st edge of DATA. Add delay tacc.
  4. Select 1st edge of DATA and 4th rising edge of CLOCK.
  5. Add Constraint. Select Max-Min Type. Add constraint tsetup.
  6. Select 4th rising edge of CLOCK and 2nd edge of ADD. Add delay tclk2q.
  7. Select 4th rising edge of CLOCK and 2nd edge of CS*. Add previously used delay tclk2q
  8. Select 4th rising edge of CLOCK and 2nd edge of DATA. Add previoulsy used delay tclk2q
  9. Select 4th rising edge of CLOCK and 2nd edge of DATA. Select Max-Min. Add constraint thold.
  10. Select 4th rising edge of CLOCK and 2nd edge of RD_STROBE*. Add delay tclk2q
  11. Click in delay and contraint labels in diagram and then use the arrow key combinations to position the labels.

Adding the StateBars¶

• To add a StateBar, Add Menu -> StateBar or Ctrl-4

  1. Select 1st rising edge of CLOCK. Add StateBar S1 using dialog.
  2. Select 2nd rising edge of CLOCK. Add StateBar S2 using dialog already open.
  3. Select 3nd rising edge of CLOCK. Add StateBar S3 using dialog already open.
  4. Select 4nd rising edge of CLOCK. Add StateBar S1 using dialog already open.

Timing Analysis¶

You could increase the CLOCK frequency or change any of the delays to quickly check for constraint violations. This will indicate problems with fast clock rates or slower parts. Drag a Delay or Constraint edge to see the results immediately.

Manuals¶

• Reference.
• Scripting.

Application Notes¶

• Generating Timing Diagrams from Verilog and VHDL Simulations.
• Introduction to Timing Analysis.

Why won’t it start?¶

In the settings directory, there is a file called ta_open_files_list. This file contains the names of the timing diagram files that were left open when you last closed the program. If one of the files is missing or it was moved, this would cause the program to hang when starting. If one of the files is saved on a network drive and the network drive is not mapped or not responding, this would also cause the program to hang when starting.

How do I start the program from the command line?¶

You might want to start the program from the command line if your developing python scripts and want to see the debug information that is output to the shell.

Refer to getting_started.

You might also want to start the program from the command line and specify more heap memory if your converting larger vcd waveforms diagrams to timing diagrams.

Refer to Working with VCD Files

How do I perform a timing analysis?¶

In older versions of the program, you had to select the analysis mode using a menu. You had a choice of min, typ, max, or margins and you couldn’t edit the timing diagram when margins was selected. Now, it is always in the margins mode and you can edit the diagram. You can also move the min and max edges in an edge margin or delay with the mouse or arrow keys in combination with Crtl, Shft, and Alt keys.

Basic procedure for timing analysis:

• Add delays that represent real part delays specified by the manufacturer.
• Add constraints that represent real part constraints specified by the manufacturer. Constraint errors are shown in orange, otherwise they are gray. A report of the delays and constraints will be coming a new version soon.
• Move the edges that connect to one of the delays in a path with the mouse and see how it affects the constraint. If there is a constraint error, you can move one of the edges to the left decreasing the delay time. If the constraint error is eliminated (color changed to gray), a faster part with less delay is one way to fix the problem. If there isn’t a constraint error and you move one of the edges increasing the delay time and a constraint error occurs, then you might be able to use a slower part with more delay and still meet the timing requirements.

What new features are planned¶

• generate reports listing actual delays and constraint values
• VCD output from timing diagram for use as simulator test vectors.
• bus enumerations for state machines
• Min/Max VCD diagrams for gate level simulation results
• more timing diagram generator scripts (common bus protocols)
• Define transactions. Copy and paste transactions
• Printing diagrams.

What improvements are planned¶

• change to individual User Delay and User Constraint panels.
• edit TimeWarps.
• generate timing diagrams directly from SystemVerilog app note
• generate timing diagrams directly from SystemC app note
• multi line text labels
• horizontal dividers to label groups of signals
• statebar grid shows vertical bars on all rising or falling clock edges
• output python script commands instead of command text.
• User guide and intro to timing analysis app note

What known issues will be addressed¶

• larger bus values. You can specifiy bus values greater than 32 bits, but any math functions are limited to 32 bit signed numbers.
• arrows don’t look right when delays are very small
• same constraint/delay name shown multiple times in gui combobox
• when bus values are separated by a timewarp, you can not edit the value on the left
• lines are not aligned to the edges for 0.0 rise and fall times
• undo “delete signal” does not bring the signal back sometimes
• undo moving objects sometimes don’t go back to the original position
• text labels are drawn below the image boundaries when signal heights are increased
• colors in image do not match the signal line and edge colors
• SaveAs adds multiple file extensions to the file name when “All Files” filter is selected

I’m having other problems, what should I do?¶

If your problem is not shown in the list above, send an email that includes a dump of the command line text logs.

Start the program from the command line as described in getting started, copy the information that is displayed in the shell window, and send to timinganalyzer@gmail.com with an explanation of the issue your having.